A lot of technologies use narrow poly-silicon stripes as a controlling gate to switch the current between source and drain of a MOSFET. As the area of the gate poly silicon dominantly determines the gate charge, it may be desirable in one embodiment to have small stripes as this allows low gate driving losses, low delay times, and, therefore, a high efficiency in applications. However, especially when using very small stripes the effective resistance of these stripes and, therefore, the effective gate resistance of the device get comparably high. The effective gate resistance which is a function of the poly silicon sheet resistance depends on the doping level of the poly silicon which is limited by the solubility of the doping material. The thickness of the gate poly-silicon layer cannot be increased by any order, as a too big thickness would lead to an undesired high topology which would make the process much more complex. Therefore the sheet resistance of an n-doped poly silicon layer of 600 nm thickness cannot be considerable lower than 8-10 ohm/sq. A high effective gate resistance leads to increased switching losses and to undesired inhomogeneous switching across the chip which might end-up in oscillations or in reduced device ruggedness in worst-case.
Another drawback of the small width of the poly silicon stripes is an increased on-resistance because of the JFET effect. Between two opposite p-bodies, a depletion region builds-up during the on-state of the device which is narrowing the current path and, therefore, increases the on-state resistance (Rdson). This is the so-called JFET effect. It is obvious that this effect is more pronounced with a small width of the poly silicon stripes as the p-bodies are usually implanted by using the poly-silicon openings as a mask.
FIG. 1 shows a conventional super-junction structure for explanation purposes. The device as shown in FIG. 1 has a semiconductor body with a compensation area comprising p-regions (p-columns) 130 and n-regions (n-columns) 134. The compensation region is connected to a MOS transistor cell comprising a source region 118, a body region 138 and a controlling gate 114. An insulating structure 140, electrically isolates the gate 114 from the body region 138, the source region 118, the n-regions (n-columns) 134 and a metallization layer 110. And a part of the insulating structure 140 may act as gate insulating layer. The drain 128 of the transistor is connected to a highly doped substrate 124. Between the substrate and the compensation area a buffer layer 126 is located. The source contacts are electrically connected by the metallization layer 110. The drain contact is built at the device backside and is covered with metallization 128.
Modern super-junction devices are featuring lower and lower pitch sizes. This trend is driven either by the reduction of Eoss which allows lower switching losses, and, even more, by the reduction of the on-resistance (Rdson) per chip area. On the one hand, a low Rdson per chip area is the major lever to reduce chip costs, and, on the other hand, it allows to provide lower Rdson values for a given package size.
A reduction of the Rdson per chip area automatically leads to narrower contact-holes for the source contact. Voidless filling of such narrow contact-holes with metal is nearly impossible. Therefore usually a plug process (e.g. Poly-silicon or Wolfram) is used. Today only a plug-process solely or an Anti-JFET implant solely are used.